Higher speed, smaller size and lower power are primary circuit design objectives. CMOS circuits have inherently lower power with higher performance than other NMOS or PMOS and, in many applications, bipolar circuits. However, CMOS circuits tend to be much larger than a corresponding NMOS or PMOS circuit. Therefore, in some instances pass gates are employed, sparingly, to reduce circuit size without increasing power or losing speed. Unfortunately, pass gates do not pass both logic levels fully, exhibit a large input capacitance (which includes the pass gate's load) and, the number of series connected pass gates must be limited.
Pass gates do not pass both logic levels fully because each pass gate, which is an FET, has a minimum gate to source turn-on voltage V.sub.T that must be maintained to keep the pass gate turned on. Thus, a PFET with its gate grounded, can pass a full high level, V.sub.H, but cannot pull down an output lower than V.sub.Tp. An NFET pass gate, on the other hand, with its gate at V.sub.H can fully pass a low providing OV at its output but, passes no higher than V.sub.H -V.sub.Tn. Thus, as a signal is propagated through series connected PFET and NFET pass gates, its levels are attenuated from V.sub.H and OV to V.sub.H - V.sub.Tn, and V.sub.Tp. This attenuation severely reduces circuit noise margin, increases power dissipation in subsequent circuits and may slow overall circuit performance somewhat. Noise margin is reduced because the signal voltage swing is reduced. Power dissipation is increased because subsequent stages driven by the attenuated signal have higher flush current. Flush current results when in an inverter, for example, both the PFET and the NFET are on. So, instead of being directed to or from a load, current is flowing between V.sub.H and ground through both devices. Because pass gate pass attenuated signals, one or both FETs may not turn completely off, allowing continuous current to flow through the following stage. Subsequent circuit performance is slowed both because the drive to the following stage's PFETs and NFETs is reduced from the pass gate's reduced drive voltage and because drive current from that following stage is diverted as flush current instead of for driving its load.
Input capacitance, which determines circuit fan-in, is higher for pass gate circuits than for other circuit types for two reasons. First, instead of just FET gate capacitance, the input capacitance is channel capacitance source diffusion capacitance and drain diffusion capacitance. These three types of capacitance are normally much higher than FET gate capacitance. Second, because the pass gate is on, a substantial portion of the pass gate's load capacitance is passed back through the pass gate to the input.
The number of series connected pass gates must be limited, because, for the foregoing reasons, signal degradation, as well as delays become severe. Loads at each stage coupled with pass gate channel resistance form an RC network to filter the propagating signal. The signal loss at each stage exacerbates the problems of single stage attenuation. The filtered signal must be redriven frequently or intolerable signal loss occurs.
Prior art approaches to these problems with pass gate logic have been primarily to buffer pass gate stages periodically, with, for example, an inverter at the passgate's input or output. However, buffering adds unwanted additional stage delay. Another prior art approach is to use a single FET type for pass gates and to reinforce the resulting attenuated logic levels, at each pass gate output. Unfortunately, level reinforcement, places further constraints on the number of series connected pass gates. This additional constraint is required because, eventually, with enough series connected passgates, the gates effectively become a voltage divider. Some of the final stages would not switch at all, with intervening stages pulled only to intermediate levels.